1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a floating body memory having leakage shield patterns and a method of fabricating the same.
2. Description of the Related Art
In general, a semiconductor memory includes a cell region and a peripheral circuit region. Memory cells are located in the cell region, and driving devices necessary to operate the memory cells, such as transistors, are located in the peripheral circuit region.
Dynamic random access memory (DRAM) cells, which is a type nonvolatile memory device, are widely used as the memory cells. Typically, DRAM cells include one capacitor, one transistor and interconnections. However, the trend toward lightweight, thin, short and small electric appliances has created a demand for more highly integrated DRAM cells. In other words, a great number of DRAM cells must be formed in a restricted space. However, highly integrating the DRAM cells presents a number of difficulties.
For example, the capacitor of a DRAM cell includes an upper electrode, a lower electrode and a capacitor dielectric layer. The upper and lower electrodes have an overlapping region. The capacitor dielectric layer is interposed between the upper electrode and the lower electrode. The capacitance of the capacitor is directly proportional to the size of the overlapping region, and inversely proportional to the thickness of the capacitor dielectric layer. Therefore, the capacitor requires a minimum area based on capacitance requirements.
To address this limitation, single transistor floating body DRAM cells have been researched. A single transistor floating body DRAM cell stores data in a floating body, and does not use the capacitor. Therefore, the single transistor floating body DRAM cell has a more advantageous structure for high integration than the capacitor DRAM cell.
The single transistor floating body DRAM cell includes a buried insulating layer on a semiconductor substrate. An isolation layer, a floating body, and source and drain regions are positioned on the buried insulating layer. A gate dielectric layer and a gate electrode are sequentially stacked on the floating body. The floating body is electrically isolated by the isolation layer, the buried insulating layer, the gate dielectric layer, and the source and drain regions.
The single transistor floating body DRAM cell stores and reads data using a floating body effect. Excess holes produced due to impact ionization are accumulated in the floating body. The excess holes accumulated in the floating body change a threshold voltage (Vt). Accordingly, the amount of current flowing between the source and drain regions depends on the amount of accumulated excess holes.
However, the excess holes accumulated in the floating body are erased in time through the source and drain regions. Delay in erasing the excess holes is favorable for extending the data retention time of the single transistor floating body DRAM cell. Therefore, extending the time before which the excess holes are erased can improve the data retention characteristics of the single transistor floating body DRAM cell.
Meanwhile, the transistor in the peripheral circuit region requires high-speed operation characteristics. When the source and drain regions of the transistor have large junction areas, a junction capacitance of the source and drain regions increases, which leads to a decrease in the operating speed of the transistor. Therefore, reducing the junction capacitance of the source and drain regions can improve the operating speed characteristics of the single transistor floating body DRAM cell.
An example of a floating body memory is disclosed in U.S. Patent Application Publication No. 2006/0046408 to OHSAWA, entitled “Semiconductor Integrated Device.” According to OHSAWA, an NMOSFET, a PMOSFET and a floating body cell (FBC) are provided on a silicon-on-insulator (SOI) substrate.